1. Field of the Invention
The present invention relates to semiconductor integrated circuits.
Specifically, the present invention relates to a semiconductor integrated circuit that decreases its power consumption by blocking a leakage current of a transistor in the stopped state.
2. Description of the Related Art
As a technique for decreasing the power consumption of a CMOS integrated circuit while preventing the lowering of the operating speed of MOS transistors, a multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is known (refer to e.g. Japanese Patent Laid-Open Hei No. 6-29834).
For a logic circuit block to which the MTCMOS technique is applied, a virtual supply voltage line and a virtual reference voltage line are provided, and the logic circuit block is connected between these lines. The virtual supply voltage line and a supply voltage line are connected to each other via a switch transistor, and the virtual reference voltage line and a reference voltage line are also connected to each other via a switch transistor.
To the supply voltage line, a high-level voltage is applied via a power supply pad from a system power supply or the like outside the CMOS integrated circuit. To the reference voltage line, a low-level voltage (e.g. ground potential) is applied via a power supply pad from the system power supply or the like outside the CMOS integrated circuit.
The switch transistors are in the on-state when the logic circuit block to which the MTCMOS technique is applied is in the operating state, and are in the off-state when it is in the stopped state.
The threshold voltages of p-type MOS transistor and n-type MOS transistor used as the switch transistors are higher than those of p-type MOS transistor and n-type MOS transistor included in the logic circuit block.
Therefore, when the logic circuit block is in the stopped state, the leakage currents of the MOS transistors included in the logic circuit block are blocked by the switch transistors. On the other hand, when the logic circuit block is in the operating state, the MOS transistors included in the logic circuit block operate at high speed.
In another configuration of a logic circuit block to which the MTCMOS technique is applied, either one of a virtual supply voltage line and a virtual reference voltage line is provided. A switch transistor is used for the connection between the virtual supply voltage line and a supply voltage line or between the virtual reference voltage line and a reference voltage line.
As described above, switch transistors having high threshold voltages are included in a CMOS integrated circuit employing the MTCMOS technique. Therefore, the circuit layout of this CMOS integrated circuit is more difficult compared with a circuit for which the MTCMOS technique is not used. However, a layout method that can alleviate the difficulty has been proposed (refer to e.g. Japanese Patent Laid-Open No. 2005-259879).
However, the CMOS integrated circuit for which the MTCMOS technique is used involves the case in which a logic circuit block in the stopped state and a logic circuit block in the operating state simultaneously exist as logic circuit blocks to which the MTCMOS technique is applied. In addition, a logic circuit block also exists that does not employ the MTCMOS technique and is connected directly to supply voltage line and reference voltage line so as to be constantly in the operating state.
When the switch transistors for blocking leakage currents are turned on and the logic circuit block in the stopped state is switched to the operating state, a sudden current (hereinafter, referred to as an inrush current) temporarily flows in the transient state of this switching from the stopped state to the operating state. It is known that this inrush current leads to voltage changes on the supply voltage line and the reference voltage line and hence causes the erroneous operation and the lowering of the operating speed of the logic circuit blocks in the operating state.
A technique has been proposed to suppress the peak of this inrush current. In this technique, for a logic circuit block to which the MTCMOS technique is applied, plural switch transistors are used for each of the connections between a virtual supply voltage line and a supply voltage line and between a virtual reference voltage line and a reference voltage line, and these switch transistors are sequentially turned on with time lag (refer to e.g. Japanese Patent Laid-Open No. 2003-289245).
This method, in which plural switch transistors used for each of the connections between a virtual supply voltage line and a supply voltage line and between a virtual reference voltage line and a reference voltage line are turned on with time lag, is effective to suppress the peak of the inrush current. However, it takes a long time for this method to switch the state of the logic circuit block from the stopped state to the operating state. Therefore, this method is not preferable for a circuit desired to return to the operating state at high speed.